A comparison between lattice, cascade and direct form FIR filter structures by using a FPGA bit-serial distributed arithmetic implementation

摘要

Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. M. M. Peiró, J. Valls, T. Sansaloni, A. P. Pascual, and E. I. Boemo, "A comparison between lattice, cascade and direct form FIR filter structures by using a FPGA bit-serial distributed arithmetic implementation", in 6th IEEE International Conference on Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99, 2009, p. 241 - 244